By utilizing recent improvements in simulation technology, circuit synthesis technology, and a hardware description language typified by VHDL (VHSIC (Very High Speed Integrated Circuit) Hardware Description Language) and Verilog-HDL, many designers of System-on-Chip (SoC) who realize an electronic circuit system on a chip as a large scale integrated circuit describe an operation specification of the circuit system by the hardware description language, and verify by a simulation CAD (HDL simulator) whether descriptions of this operation specification satisfy a requested function as system. Thereafter, these designers perform circuit synthesis, by using a synthesis tool, to logic circuits as gate-level description corresponding to the operation specification descriptions.
The designers seldom participate in all processes for designing the circuit system because there are strong demands recently to shorten a period necessary for designing the circuits. In a situation where the circuit system to be designed is divided for each of its functions, the designers often procure circuit design data at a hardware description language level as virtual components and combine these virtual components to assemble the circuit system. The circuit design data is often provided from vendors in specialized technical fields.
With an increase in system scale (circuit scale) and elevation in functional level of the circuit system, varieties of the virtual components to be combined tend to increase. Furthermore, the number of vendors offering the virtual components tends to increase. Accordingly, the system designers cannot ignore variations of qualities of circuits and operation verification standards for virtual components. Furthermore, because of high performance of the virtual components and competition among the vendors, concealment of internal information in the virtual components is promoted, that is, the virtual components tend to be made in the form of a black box. The system designers then have difficulty verifying the qualities of the virtual components.
Operation verification is very important before the manufacturing of LSI because it is very difficult to correct the design data for the LSI after manufacture. It is necessary to verify by a simulator or the like in a circuit design step before manufacturing whether a virtual component unit or the whole of the circuit system composed of a plurality of procured virtual components operate normally. When it is proved that the circuit system does not operate normally in the simulation, a part of the circuit causing the abnormal operation in this step should be detected and corrected.
Usually, the virtual components are guaranteed, by the vendors who are the providers thereof, to operate normally and are sold. For the above-described reasons users who are the system designers demand to verify the circuit system in their own way. Conventionally, when each of the users verifies a unit of the virtual component that they procured, the user prepares a driving circuit for use in verifying the virtual component, based on a specification (usually, only a specification concerning input/output terminals of the virtual components) and external conditions under which the virtual component operates within a limited range disclosed by the provider of the virtual component. Then, by use of a simulator, the user allows the virtual component to operate alone, thus verifying the virtual component. At this time, if the user judges operation of the virtual component to be abnormal, the user needs to detect a part where the problem occurred and to investigate a cause of the abnormality of the virtual component. To investigate the cause thereof, the user must perform an internal analysis of the virtual component thoroughly.
However, due to the high performance of the virtual component and the concealment of the internal information, the user is in a very difficult situation in performing the internal analysis for the virtual component and in detecting the spot where the abnormality originates. Furthermore, even if the driving circuit for use in verifying the virtual component made by the user independently causes the abnormality practically and the virtual component itself shows no abnormality, the user often performs an unnecessary internal analysis of the virtual component to detect the cause of the abnormality in consequence.
When the operation abnormality of the virtual components is confirmed in a step where the virtual components are combined into a system, the user has to perform an internal analysis of virtual components to determine the virtual component among the plurality of virtual components, which caused the abnormality, and to investigate the cause of the abnormality. However, for the above-described reason, it is difficult for the user to perform the internal analysis for each of the virtual components, and the user has to spare a considerable length of time to determine an abnormal virtual component among the virtual components and to take countermeasures to deal with the abnormality of the virtual component.
As described above, when an abnormal operation occurs in verifying the virtual component unit and the whole of the circuit system, the internal analysis for each virtual component is inevitable. However, due to the high performance of the virtual component and the concealment of the internal information, the internal analysis of the virtual component and the determination of the original spot in the virtual component where the abnormality occurred are becoming very difficult. Furthermore, the internal analysis of the virtual component requires enormous time and labor owing to its complexity, and a problem comes to occur in which advantages of shortening a design period, which is an original goal, cannot be obtained, the advantages for the user being first achieved by the virtual components procurement from the vendors.